HD64F2638F20J Datasheet, PDF (556/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 13 Serial Communication Interface (SCI)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
16 clocks
8 clocks
0
7
15 0
7
Internal basic
clock
15 0
Receive data
(RxD)
Synchronization
sampling timing
Start bit
D0
D1
Data sampling
timing
Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode
Thus the reception margin in asynchronous mode is given by formula (1) below.
1
| D – 0.5 |
M = | (0.5 –
) – (L – 0.5) F –
(1 + F) | × 100%
2N
N
Where
M : Reception margin (%)
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
... Formula (1)
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by
formula (2) below.
When D = 0.5 and F = 0,
1
M = (0.5 –
) × 100%
2 × 16
= 46.875%
... Formula (2)
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Page 506 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010