HD64F2638F20J Datasheet, PDF (659/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
I²C bus interface
(Master transmit mode)
Other device
(Master transmit mode)
I²C bus interface
(Slave receive mode)
• Arbitration is lost
• The AL flag in ICSR is set to 1
S
SLA R/W A
DATA1
Transmit data match
Transmit timing match
Transmit data does not match
S
SLA
R/W A
DATA2
A
DATA3
A
S
SLA
R/W A
• Receive address is ignored
SLA
R/W A
• Automatically transferred to slave
receive mode
• Receive data is recognized as an
address
• When the receive data matches to
the address set in the SAR or SARX
register, the I²C bus interface operates
as a slave device.
Data contention
DATA4
A
Figure 15-27 Diagram of Erroneous Operation when Arbitration is Lost
Though it is prohibited in the normal I²C protocol, the same problem may occur when the
MST bit is erroneously set to 1 and a transition to master mode is occurred during data
transmission or reception in slave mode. In multi-master mode, pay attention to the setting of
the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register
should be set to 1 according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
(b) Set the MST bit to 1.
(c) To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
• Notes on Wait Operation in Master Mode
During master mode operation using the wait function, when the interrupt flag IRIC bit is
cleared from 1 to 0 between the falling edge of the 7th clock cycle and the falling edge of the
8th clock cycle, in some cases no wait is inserted after the falling edge of the 8th clock cycle
and the clock pulse of the 9th clock cycle is output continuously.
Observe the following with regard to clearing the IRIC flag while using the wait function.
At the rising edge of the 9th clock cycle, set the IRIC flag to 1 and then clear it to zero before
the rising edge of the 1st clock cycle (while the value of the BC2 to BC0 counter value is 2 or
greater).
If clearing of the IRIC flag is delayed by interrupt processing or the like and the BC counter
value reaches 1 or 0, confirm that the SCL pin state is low-level after the BC2 to BC0 counter
has reached 0 and then clear the IRIC flag. (See figure 15.28.)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 609 of 1458