HD64F2638F20J Datasheet, PDF (36/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

10.2.5 Timer Status Register (TSR)................................................................................ 338
10.2.6 Timer Counter (TCNT)........................................................................................ 342
10.2.7 Timer General Register (TGR) ............................................................................ 343
10.2.8 Timer Start Register (TSTR) ............................................................................... 344
10.2.9 Timer Synchro Register (TSYR) ......................................................................... 345
10.2.10 Module Stop Control Register A (MSTPCRA) ................................................... 346
10.3 Interface to Bus Master ..................................................................................................... 347
10.3.1 16-Bit Registers ................................................................................................... 347
10.3.2 8-Bit Registers ..................................................................................................... 347
10.4 Operation .......................................................................................................................... 349
10.4.1 Overview ............................................................................................................. 349
10.4.2 Basic Functions.................................................................................................... 350
10.4.3 Synchronous Operation........................................................................................ 356
10.4.4 Buffer Operation .................................................................................................. 358
10.4.5 Cascaded Operation ............................................................................................. 362
10.4.6 PWM Modes........................................................................................................ 364
10.4.7 Phase Counting Mode.......................................................................................... 370
10.5 Interrupts........................................................................................................................... 377
10.5.1 Interrupt Sources and Priorities ........................................................................... 377
10.5.2 DTC Activation ................................................................................................... 379
10.5.3 A/D Converter Activation.................................................................................... 379
10.6 Operation Timing.............................................................................................................. 380
10.6.1 Input/Output Timing ............................................................................................ 380
10.6.2 Interrupt Signal Timing ....................................................................................... 384
10.7 Usage Notes ...................................................................................................................... 388
Section 11 Programmable Pulse Generator (PPG) .................................................... 399
11.1 Overview........................................................................................................................... 399
11.1.1 Features................................................................................................................ 399
11.1.2 Block Diagram..................................................................................................... 400
11.1.3 Pin Configuration................................................................................................. 401
11.1.4 Registers .............................................................................................................. 402
11.2 Register Descriptions ........................................................................................................ 403
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 403
11.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 404
11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 405
11.2.4 Notes on NDR Access ......................................................................................... 405
11.2.5 PPG Output Control Register (PCR) ................................................................... 407
11.2.6 PPG Output Mode Register (PMR) ..................................................................... 409
11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 412
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REJ09B0103-0800 Rev. 8.00
May 28, 2010