HD64F2638F20J Datasheet, PDF (7/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Main Revisions in This Edition
Item
Page
1.3.1 Pin Arrangement 10
Figure 1-3 Pin
Arrangement of
H8S/2638 Group and
H8S/2630 Group
(FP-128B: Top View)
Revision (See Manual for Details)
Figure amended
Notes: 1.
2.
3.
4.
Connect a 0.1 µF capacitor between VCL and VSS (close to the pins).
Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask
and W-mask versions.
These functions cannot be used with the other versions.
See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2.
These pins are used for the I²C bus interface.
The I²C bus interface is available as an option. The product equipped with the I²C bus interface is
the W-mask version.
The FWE pin is for compatibility with the flash memory version.
The FWE pin is a NC pin in the mask ROM versions.
In the mask ROM version, the FWE pin must be left open or be connected to Vss.
(U-Mask Version)
(W-Mask Version)
64F2638F20
H8S/2638
INDEX
64F2638F20
H8S/2638
U
INDEX
64F2638F20
H8S/2638
W
INDEX
(U-Mask Version)
(W-Mask Version)
64F2630F20
H8S/2630
INDEX
64F2630F20
H8S/2630
U
INDEX
64F2630F20
H8S/2630
W
INDEX
1.4 Differences
between H8S/2636,
H8S/2638, H8S/2639,
H8S/2630, H8S/2635,
and H8S/2634
23 to 24 Table amended
Part No.
Table 1-4 Comparison
of Product
Specifications
24
Note amended
Model
ROM
RAM
Note: * For details of the H8S/2639, H8S/2635, and
H8S/2634 clock pulse generator, see section 22B,
Clock Pulse Generator (H8S/2639 Group, H8S/2635
Group).
2.4.3 Control
38
Registers
(3) Condition-Code
Register (CCR)
Description amended
Some instructions leave some or all of the flag bits unchanged.
For the action of each instruction on the flag bits, refer to
appendix A.1, Instruction List.
Bit 0—Carry Flag (C):
2.5.2 Memory Data 41
Formats
Figure 2-11 Memory
Data Formats
Figure replaced
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page vii of l