HD64F2638F20J Datasheet, PDF (52/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 1 Overview
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Table 1-1 Overview
Item
Specification
CPU
• General-register machine
⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
• High-speed operation suitable for realtime control
⎯ Maximum clock rate: 20 MHz
⎯ High-speed arithmetic operations
8/16/32-bit register-register add/subtract : 50 ns
16 × 16-bit register-register multiply
: 200 ns
16 × 16 + 42-bit multiply and accumulate : 200 ns
32 ÷ 16-bit register-register divide
: 1000 ns
• Instruction set suitable for high-speed operation
⎯ Sixty-nine basic instructions
⎯ 8/16/32-bit move/arithmetic and logic instructions
⎯ Unsigned/signed multiply and divide instructions
⎯ Multiply-and accumulate instruction
⎯ Powerful bit-manipulation instructions
• CPU operating modes
⎯ Advanced mode: 16-Mbyte address space
Bus controller
• Address space divided into 8 areas, with bus specifications settable
independently for each area
• Choice of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Direct connection to burst ROM supported
PC break controller •
(This function is not _•
implemented in the
H8S/2635 Group)
Supports debugging functions by means of PC break interrupts
Two break channels
Data transfer
•
controller (DTC)
•
(This function is not
implemented in the
H8S/2635 Group) •
Can be activated by internal interrupt or software
Multiple transfers or multiple types of transfer possible for one activation
source
Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
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REJ09B0103-0800 Rev. 8.00
May 28, 2010