HD64F2638F20J Datasheet, PDF (125/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 2 CPU
2.9.5 Port H and J Register Access Timing
Accesses to port H and J registers and the on-chip motor control PWM timer module are
performed in four states. The data bus width is 8 or 16 bits depending on the internal I/O register.
Access timing for port H and J registers and the on-chip motor control PWM timer module is
shown in figure 2-24, and the pin states are shown in figure 2-25.
φ
Internal address
bus
Read
Read signal
Internal data
bus
Write
Write signal
Internal data
bus
Bus cycle
T₁
T₂
T₃
T₄
Address
Read data
Write data
Figure 2-24 Access Cycle for Ports H and J Registers and On-Chip Motor Control
PWM Timer Module
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 75 of 1458