HD64F2638F20J Datasheet, PDF (778/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 19 Motor Control PWM Timer
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bits 9 to 0—Duty (DT): Bits 9 to 0 set the PWM output duty according to the values in bits 9 to 0
in the buffer register that is transferred by a PWCYR2 compare match. A high level (or a low level
when the corresponding bit in PWPR2 is set to 1) is output from the time PWCNT2 is cleared by a
PWCYR2 compare match until a PWDTR2 compare match occurs. When all the bits are 0, there
is no high-level output period (no low-level output period when the corresponding bit in PWPR2
is set to 1).
PWCNT2
(lower 10 bits)
PWCYR2
(lower 10 bits)
PWDTR2
(lower 10 bits)
PWM output
0
1
Compare match
M−2 M−1 M
N
M
N−1 0
Figure 19-6 Duty Register Compare Match (OPS = 0 in PWPR2)
PWCNT2
(lower 10 bits)
0
1
PWCYR2
(lower 10 bits)
N
PWDTR2
(lower 10 bits)
M
PWM output
(M = 0)
PWM output
(0 < M < N)
PWM output
(N ≤ M)
N−2 N−1 0
Figure 19-7 Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR2)
Page 728 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010