HD64F2638F20J Datasheet, PDF (442/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T₂ state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
data prior to the write.
Figure 10-52 shows the timing in this case.
TGR write cycle
T₁
T₂
φ
Address
Buffer register
address
Write signal
Compare
match signal
Buffer
register
Buffer register write data
N
M
TGR
N
Figure 10-52 Contention between Buffer Register Write and Compare Match
Page 392 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010