HD64F2638F20J Datasheet, PDF (595/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
A two-channel I²C bus interface is available as an option in the H8S/2638, H8S/2639, and
H8S/2630 (the product equipped with the I²C bus interface is the W-mask version). Observe the
following notes when using this option.
A “W” is added to the part number in products in which this optional function is used.
Examples: HD64F2638WF*
Note: * When the optional function is used in a U-mask version, “U” is replaced with “W”.
Example: HD64F2638UF → HD64F2638WF
15.1 Overview
A two-channel I²C bus interface is available for the H8S/2638, H8S/2639, and H8S/2630 as an
option. The I²C bus interface conforms to and provides a subset of the Philips I²C bus (inter-IC
bus) interface functions. The register configuration that controls the I²C bus differs partly from the
Philips configuration, however.
Each I²C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer
data, saving board and connector space.
15.1.1 Features
• Selection of addressing format or non-addressing format
⎯ I²C bus format: addressing format with acknowledge bit, for master/slave operation
⎯ Serial format: non-addressing format without acknowledge bit, for master operation only
• Conforms to Philips I²C bus interface (I²C bus format)
• Two ways of setting slave address (I²C bus format)
• Start and stop conditions generated automatically in master mode (I²C bus format)
• Selection of acknowledge output levels when receiving (I²C bus format)
• Automatic loading of acknowledge bit when transmitting (I²C bus format)
• Wait function in master mode (I²C bus format)
⎯ A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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