HD64F2638F20J Datasheet, PDF (953/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 22A Clock Pulse Generator
(H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
Section 22A Clock Pulse Generator
(H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
22A.1 Overview
The chip has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock
oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL
circuit in the CPG. Frequency changes are performed by software by means of settings in the
system clock control register (SCKCR) and low-power control register (LPWRCR).
22A.1.1 Block Diagram
Figure 22A-1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
System
clock
oscillator
LPWRCR
STC1, STC0
PLL circuit
(×1, ×2, ×4)
φSUB
Clock
selection
circuit
SCKCR
SCK2 to SCK0
Medium-
speed
clock divider
φ/2 to
φ/32
φ
Bus
master
clock
selection
circuit
OSC1^*
OSC2^*
Subclock
oscillator
Waveform
Generation
Circuit
System clock Internal clock to
to φ pin supporting modules
Bus master clock
to CPU and DTC
Legend:
WDT1 count clock
LPWRCR: Low-power control register
SCKCR: System clock control register
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and
W-mask versions only.
These functions cannot be used with the other versions.
See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2.
Figure 22A-1 Block Diagram of Clock Pulse Generator
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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