HD64F2638F20J Datasheet, PDF (1472/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix C I/O Port Block Diagrams
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagrams
Reset
R
Q
D
P1nDDR
C
WDDR1
Reset
R
Q
D
P1nDR
System controller
C
Address output enable
P1n
WDR1
*¹
From internal address bus
PPG module^*2
Pulse output enable
Pulse output
RDR1
TPU module
Output compare
Output/PWM output enable
Output compare output/
PWM output
RPOR1
Input capture input
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
n = 0 or 1
Notes: 1. Priority order: Address output > output compare output/PWM output > pulse output > DR output
2. The PPG module is not implemented in the H8S/2635 Group.
Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11)
Page 1422 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010