HD64F2638F20J Datasheet, PDF (858/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21B ROM
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
21B.6 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 21B-6.
Table 21B-6 Register Configuration
Register Name
Abbreviation R/W
Initial Value Address^*1
Flash memory control register 1
FLMCR1^*4
R/W
Flash memory control register 2
FLMCR2^*4
R
Erase block register 1
EBR1^*4
R/W
Erase block register 2
EBR2^*4
R/W
RAM emulation register
RAMER^*4
R/W
Flash memory power control register FLPWCR^*4
R/W
H'00^*2
H'00
H'00^*3
H'00^*3
H'00
H'00^*3
H'FFA8
H'FFA9
H'FFAA
H'FFAB
H'FEDB
H'FFAC
Notes: 1. Lower 16 bits of the address.
2. When a high level is input to the FWE pin, the initial value is H'80.
3. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in
FLMCR1 is not set, these registers are initialized to H'00.
4. FLMCR1, FLMCR2, EBR1, and EBR2, RAMER, and FLPWCR are 8-bit registers.
Use byte access on these registers.
Page 808 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010