HD64F2638F20J Datasheet, PDF (304/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 9 I/O Ports
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
• Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
Port A Data Register (PADR)
Bit
:
7
6
5
4
3
—
—
—
— PA3DR
Initial value : Undefined Undefined Undefined Undefined 0
R/W
:—
—
—
—
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to
PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port A Register (PORTA)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
Initial value : Undefined Undefined Undefined Undefined
PA3
—^*
PA2
—^*
PA1
—^*
PA0
—^*
R/W
:—
—
—
—
R
R
R
R
Note: * Determined by state of pins PA3 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA3 to PA0) must always be performed on PADR.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as
PADDR and PADR are initialized. PORTA retains its prior state in software standby mode.
Page 254 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010