HD64F2638F20J Datasheet, PDF (232/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 7 Bus Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle.
Figure 7-15 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
φ
Address bus
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
CS* (area A)
CS* (area B)
RD
Data bus
φ
Address bus
CS* (area A)
CS* (area B)
RD
Data bus
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Data
Long output _collision
floating time
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Note: * The CS signal is generated externally rather than inside the LSI device.
Figure 7-15 Example of Idle Cycle Operation (1)
Page 182 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010