HD64F2638F20J Datasheet, PDF (637/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
[8] 1 clock cycle wait time
SCL
(master output) ⁸
SDA
(slave output)
Bit 0
Data 2 _[3]
SDA
(master output)
912 3 4 56 7 8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[3]
Data 3
[12]
[12]
A
A
IRIC
IRTR
ICDR
[4] IRTR = 0
Data 1
[4] IRTR = 1
Data 2
[13] IRTR = 0 [13] IRTR = 1
Data 3
Stop condition
generated
User processing
[6] IRIC clearance
[11] IRIC clearance
[10] ICDR read (data 2)
[9] TRS set to 1
[7] ACKB set to 1
[14] IRIC clearance
[15] WAIT cleared to 0
IRIC clearance
[17] Stop condition
issued
[16] ICDR read (data 3)
Figure 15-13 Example of Master Receive Mode Stop Condition Generation Timing
(MLS = ACKB = 0, WAIT = 1)
15.3.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal.
The slave device compares its own address with the slave address in the first frame following the
establishment of the start condition issued by the master device. If the addresses match, the slave
device operates as the slave device designated by the master device.
Figure 15-14 is a flowchart showing an example of slave receive mode operation.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 587 of 1458