HD64F2638F20J Datasheet, PDF (484/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
WDT0 Input Clock Select
Description
Bit 2
CKS2
0
1
Bit 1
CKS1
0
1
0
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Clock
Overflow Period^*1 (where φ = 20 MHz)
φ/2^*2 (initial value) 25.6 µs
φ/64^*2
819.2 µs
φ/128^*2
1.6 ms
φ/512^*2
6.6 ms
φ/2048^*2
26.2 ms
φ/8192^*2
104.9 ms
φ/32768^*2
419.4 ms
φ/131072^*2
1.68 s
Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the occurrence of a TCNT overflow.
2. In the U-mask and W-mask versions, and H8S/2635 Group, φ in subactive and
subsleep modes operates as φSUB.
Page 434 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010