HD64F2638F20J Datasheet, PDF (231/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 7 Bus Controller
7.5.3 Wait Control
As with the basic bus interface, program waits can be inserted in the burst ROM interface initial
cycle (full access). See section 7.4.5, Wait Control.
Wait states cannot be inserted in the burst cycle.
7.6 Idle Cycle
7.6.1 Operation
When the chip accesses external space, it can insert a 1-state idle cycle (T_I) between bus cycles in
the following two cases: (1) when read accesses between different areas occur consecutively, and
(2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM, with a long output floating time, and
high-speed memory, I/O interfaces, and so on.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 181 of 1458