HD64F2638F20J Datasheet, PDF (1005/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the
software standby mode, watch mode, and when making a direct transition.
Bit 3
OPE
0
1
Description
In software standby mode, watch mode, and when making a direct transition, address
bus and bus control signals are high-impedance.
In software standby mode, watch mode, and when making a direct transition, the
output state of the address bus and bus control signals is retained.
(Initial value)
Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.
23B.2.2 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
3
2
1
0
PSTOP ⎯
⎯
⎯
STCS SCK2 SCK1 SCK0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
⎯
⎯
⎯
R/W
R/W
R/W
R/W
SCKCR is an 8-bit readable/writable register that performs φ clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls φ output. See section 23B.12, φ Clock Output Disable Function for details.
Bit 7
PSTOP
0
1
Description
High-Speed Mode,
Medium-Speed Mode, Sleep Mode,
Subactive Mode
Subsleep Mode
φ output (initial value) φ output
Fixed high
Fixed high
Software Standby
Mode, Watch Mode, Hardware Standby
Direct Transition Mode
Fixed high
High impedance
Fixed high
High impedance
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 955 of 1458