HD64F2638F20J Datasheet, PDF (477/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 12 Watchdog Timer
WOVI1
(Interrupt request signal)
Internal NMI
Interrupt request signal
Internal reset signal^*1
Interrupt
control _Overflow
Reset
control
Clock
Clock
select
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
φSUB/2^*2
φSUB/4^*2
φSUB/8^*2
φSUB/16^*2
φSUB/32^*2
φSUB/64^*2
φSUB/128^*2
φSUB/256^*2
TCNT
TCSR
Module bus
Bus
interface
Legend:
TCSR : Timer control/status register
TCNT : Timer counter
WDT
Notes: 1. An internal reset signal can be generated by setting the register
The reset thus generated is a reset
2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available
only in the U-mask and W-mask versions, and H8S/2635 Group only.
Figure 12-1 (b) Block Diagram of WDT1
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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