HD64F2638F20J Datasheet, PDF (706/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 Controller Area Network (HCAN)
Item
fCLK
BRP
TSEG1
TSEG2
Set Values
20 MHz
0 (B'000000)
4 (B'0100)
3 (B'011)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Actual Values
—
System clock × 2
5TQ
4TQ
1-bit time
1-bit time (8 to 25 time quanta)
SYNC_SEG
1
PRSEG
PHSEG1
Time segment 1
(TSEG1)*
4 to16
PHSEG2
Time segment 2
(TSEG2)*
2 to 8
Quantum
Legend:
SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus (Normal bit
edge transitions occur in this segment).
PRSEG: Segment for compensating for physical delay between networks.
PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended
when synchronization (resynchronization) is established).
PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is
shortened when synchronization (resynchronization) is established).
Note: * The time quanta values of TSEG1 and TSEG2 become the value of TSEG + 1.
Figure 16-6 Detailed Description of One Bit
HCAN bit rate calculation:
Bit rate =
f_CLK
2 × (BRP + 1) × (3 + TSEG1 + TSEG2)
fCLK: peripheral clock (φ)
Note: The BCR values are used for BRP, TSEG1, and TSEG2.
BCR Setting Constraints
TSEG1 > TSEG2 ≥ SJW (SJW = 0 to 3)
These constraints allow the setting range shown in table 16-4 for TSEG1 and TSEG2 in BCR.
Page 656 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010