HD64F2638F20J Datasheet, PDF (517/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 13 Serial Communication Interface (SCI)
The BRR setting is found from the following formulas.
Asynchronous mode:
N=
φ
64 × 2^2n–1 × B
× 10⁶ – 1
Clocked synchronous mode:
N=
φ
8 × 2^2n–1 × B
× 10⁶ – 1
Where B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is found from the following formula:
φ × 10⁶
Error (%) = { _{(N + 1) × B × 64 × 22n–1} – 1} × 100
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 467 of 1458