HD64F2638F20J Datasheet, PDF (655/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
• Notes on I²C Bus Interface Stop Condition Instruction Issuance
If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load
capacitance is large, or if there is a slave device of the type that drives SCL low to effect a
wait, issue the stop condition instruction after reading SCL and determining it to be low, as
shown below.
SCL
SDA
9th clock High period secured
VIH
As waveform rise is late,
SCL is detected as low
Stop condition
IRIC
[1] Determination of SCL = low [2] Stop condition instruction issuance
Figure 15-23 Timing of Stop Condition Issuance
• Notes on IRIC Flag Clearance when Using Wait Function
If the SCL rise time exceeds the designated duration or if the slave device is of the type that
keeps SCL low and applies a wait state when the wait function is used in the master mode of
the I²C bus interface, read SCL and clear the IRIC flag after determining that SCL has gone
low, as shown below.
Clearing the IRIC flag to 0 when WAIT is set to 1 and SCL is being held at high level can
cause the SDA value to change before SCL goes low, resulting in a start condition or stop
condition being generated erroneously.
SCL
SDA
SCL = high duration
maintained
V_IH
SCL = low detected
IRIC
[1] Judgement that SCL = low [2] IRIC clearance
Figure 15-24 IRIC Flag Clearance in WAIT = 1 Status
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 605 of 1458