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HD64F2638F20J Datasheet, PDF (57/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 1 Overview
Figure 1-1 (b) shows an internal block diagram of the H8S/2638, H8S/2639, and H8S/2630.
VCL
MD2
MD1
MD0
OSC2*1
OSC1*1
EXTAL
XTAL
PLLCAP
STBY
RES
NMI
FWE*3
PF7/ φ
PF6/ AS
PF5/ RD
PF4/ HWR
PF3/ LWR/ADTRG/IRQ3
PF0/IRQ2
PH0/PWM1A
PH1/PWM1B
PH2/PWM1C
PH3/PWM1D
PH4/PWM1E
PH5/PWM1F
PH6/PWM1G
PH7/PWM1H
PJ0/PWM2A
PJ1/PWM2B
PJ2/PWM2C
PJ3/PWM2D
PJ4/PWM2E
PJ5/PWM2F
PJ6/PWM2G
PJ7/PWM2H
Port D
Port E
H8S/2600 CPU
PLL
Interrupt controller
PC break controller
ROM
(mask ROM,
flash memory)
RAM
TPU
PPG
DTC
WDT × 2 channels
I2C bus interface
(option)
SCI × 3 channels
Motor control PWM timer
D/A converter
A/D converter
HCAN × 2 channels
Port 1
Port 4
PA3 / A19/SCK2
PA2 / A18/RxD2
PA1 / A17/TxD2
PA0 / A16
PB7 / A15/TIOCB5
PB6 / A14/TIOCA5
PB5 / A13/TIOCB4
PB4 / A12/TIOCA4
PB3 / A11/TIOCD3
PB2 / A10/TIOCC3
PB1 / A9/TIOCB3
PB0 / A8/TIOCA3
PC7 / A7
PC6 / A6
PC5 / A5
PC4 / A4
PC3 / A3
PC2 / A2
PC1 / A1
PC0 / A0
P35 / SCK1/ SCL0*2/IRQ5
P34 / RxD1/ SDA0*2
P33 / TxD1/ SCL1*2
P32 / SCK0/ SDA1*2/IRQ4
P31 / RxD0
P30 / TxD0
P93 / AN11
P92 / AN10
P91 / AN9
P90 / AN8
Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions.
These functions cannot be used with the other versions.
See section 22A.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2.
The H8S/2639 has no OSC1 and OSC2 pins.
2. These pins are used for the I2C bus interface.
The I2C bus interface is available as an option. The product equipped with the I2C bus interface is the W-mask version.
3. The FWE pin is for compatibility with the flash memory version.
The FWE pin is a NC pin in the mask ROM versions.
In the mask ROM version, the FWE pin must be left open or be connected to Vss.
Figure 1-1 (b) Internal Block Diagram of H8S/2638, H8S/2639, and H8S/2630
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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