HD64F2638F20J Datasheet, PDF (640/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Start condition issuance
SCL
(master output)
1
2
3
4
5
6
7
8
9
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W _[4]
A
RDRF
1
2
Bit 7 Bit 6
Data 1
IRIC
ICDRS
ICDRR
Interrupt
request
generation
Address + R/W
Address + R/W
User processing
[5] ICDR read [5] IRIC clearance
Figure 15-15 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0)
Page 590 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010