HD64F2638F20J Datasheet, PDF (215/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 7 Bus Controller
Table 7-3 Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR
ABWn
0
ASTn
0
1
1
0
1
WCRH, WCRL
Wn1
—
0
1
—
0
1
Wn0
—
0
1
0
1
—
0
1
0
1
Bus Specifications (Basic Bus Interface)
Bus Width
Program Wait
Access States States
16
2
0
3
0
1
2
3
8
2
0
3
0
1
2
3
7.3.3 Memory Interfaces
The chip's memory interfaces comprise a basic bus interface that allows direct connection or
ROM, SRAM, and so on, and a burst ROM interface that allows direct connection of burst ROM.
The memory interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, and an area for
which the burst ROM interface is designated functions as burst ROM space.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 165 of 1458