HD64F2638F20J Datasheet, PDF (311/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 9 I/O Ports
9.7.2 Register Configuration
Table 9-11 shows the port B register configuration.
Table 9-11 Port B Registers
Name
Abbreviation R/W
Port B data direction register
PBDDR
W
Port B data register
PBDR
R/W
Port B register
PORTB
R
Port B MOS pull-up control register PBPCR
R/W
Port B open-drain control register
PBODR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
Undefined
H'00
H'00
Address^*
H'FE3A
H'FF0A
H'FFBA
H'FF41
H'FE48
Port B Data Direction Register (PBDDR)
Bit
:
7
6
5
4
3
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
• Modes 4 to 6
The corresponding port B pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of the PBDDR bits. When pins are not used as
address outputs, setting a PBDDR bit to 1 makes the corresponding port B pin an output port,
while clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 261 of 1458