HD64F2638F20J Datasheet, PDF (1222/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
IMR0—Interrupt Mask Register
IMR1—Interrupt Mask Register
H'F816
H'FA16
Note: * This register is not available in the H8S/2635 Group.
Bit
15
14
13
12
11
IMR7 IMR6 IMR5 IMR4 IMR3
Initial value
1
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
R/W
10
IMR2
1
R/W
9
IMR1
1
R/W
HCAN0
HCAN1^*
8
⎯
0
R
Receive Message Interrupt Mask
0 Message reception interrupt request (RM1) to CPU by IRR1 enabled
1 Message reception interrupt request (RM1) to CPU by IRR1 disabled
Remote Frame Request Interrupt Mask
0 Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled
1 Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled
Transmit Overload Warning Interrupt Mask
0 TEC error warning interrupt request (OVR0) to CPU by IRR3 enabled
1 TEC error warning interrupt request (OVR0) to CPU by IRR3 disabled
Receive Overload Warning Interrupt Mask
0 REC error warning interrupt request (OVR0) to CPU by IRR4 enabled
1 REC error warning interrupt request (OVR0) to CPU by IRR4 disabled
Error Passive Interrupt Mask
0 Error passive interrupt request to CPU by IRR5 enabled
1 Error passive interrupt request to CPU by IRR5 disabled
Bus Off Interrupt Mask
0 Bus off interrupt request to CPU by IRR6 enabled
1 Bus off interrupt request to CPU by IRR6 disabled
Overload Frame/Bus Off Recovery Interrupt Mask
0 Overload frame/bus off recovery interrupt request to CPU by IRR7 enabled
1 Overload frame/bus off recovery interrupt request to CPU by IRR7 disabled
Page 1172 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010