HD64F2638F20J Datasheet, PDF (385/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 10 16-Bit Timer Pulse Unit (TPU)
10.2.4 Timer Interrupt Enable Register (TIER)
Channel 0: TIER0
Channel 3: TIER3
Bit
:
7
6
TTGE
—
Initial value :
0
1
R/W
: R/W
—
5
4
3
2
1
0
—
TCIEV TGIED TGIEC TGIEB TGIEA
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit
:
7
6
5
4
3
TTGE
—
TCIEU TCIEV
—
Initial value :
0
1
0
0
0
R/W
: R/W
—
R/W
R/W
—
2
1
0
—
TGIEB TGIEA
0
0
0
—
R/W
R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset, and in hardware standby mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 335 of 1458