HD64F2638F20J Datasheet, PDF (676/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 Controller Area Network (HCAN)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
16.2.6 Transmit Wait Cancel Register (TXCR)
The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls
cancellation of transmit wait messages in mailboxes (buffers).
TXCR
Bit: 15
14
13
12
11
10
9
8
TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 —
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bit: 7
6
5
4
3
2
1
0
TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
(x = 15 to 9, 7 to 0)
Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register (TXCR7 to TXCR1, TXCR15 to
TXCR8): These bits control cancellation of transmit wait messages in the corresponding HCAN
mailboxes.
Bit y: TXCRx
0
1
Description
Transmit message cancellation idle state in corresponding mailbox
(Initial value)
[Clearing condition]
• Completion of TXPR clearing (when transmit message is canceled
normally)
TXPR cleared for corresponding mailbox (transmit message cancellation)
(x = 15 to 1, y = 15 to 9 and 7 to 0)
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
Page 626 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010