HD64F2638F20J Datasheet, PDF (294/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 9 I/O Ports
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Port 3 Data Register (P3DR)
Bit
Initial value
Read/Write
7
6
5
⎯
⎯
P35DR
Undefined Undefined 0
⎯
⎯
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
0
P30DR
0
R/W
P3DR is an 8-bit readable/writable register, which stores the output data of port 3 pins (P35 to
P30).
P3DR is initialized to B'**000000 by a reset and in hardware standby mode. The previous state is
maintained in software standby mode.
Port 3 Register (PORT3)
Bit
7
6
5
4
3
2
1
0
⎯
⎯
P35
P34
P33
P32
P31
P30
Initial value Undefined Undefined ⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
Read/Write
⎯
⎯
R
R
R
R
R
R
Note: * Determined by the state of pins P35 to P30.
PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled.
Always carry out writing off output data of port 3 pins (P35 to P30) to P3DR without fail.
When P3DDR is set to 1, if port 3 is read, the values of P3DR are read. When P3DDR is cleared to
0, if port 3 is read, the states of pins are read out.
P3DDR and P3DR are initialized by a reset and in hardware standby mode, so PORT3 is
determined by the state of the pins. The previous state is maintained in software standby mode.
Page 244 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010