HD64F2638F20J Datasheet, PDF (587/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 14 Smart Card Interface
With the above processing, interrupt servicing or data transfer by the DTC* is possible.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in
reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI)
request will be generated.
If the DTC* is activated by an RXI request, the receive data in which the error occurred is
skipped, and only the number of bytes of receive data set in the DTC* are transferred.
For details, see Interrupt Operation and Data Transfer Operation by DTC* followings.
If a parity error occurs during reception and the PER is set to 1, the received data is still
transferred to RDR, and therefore this data can be read.
Notes: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode.
* The DTC is not implemented in the H8S/2635 Group.
Mode Switching Operation: When switching from receive mode to transmit mode, first confirm
that the receive operation has been completed, then start from initialization, clearing RE bit to 0
and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the
receive operation has been completed.
When switching from transmit mode to receive mode, first confirm that the transmit operation has
been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The
TEND flag can be used to check that the transmit operation has been completed.
Fixing Clock Output Level: When the GM bit in SMR is set to 1, the clock output level can be
fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be
made the specified width.
Figure 14-8 shows the timing for fixing the clock output level. In this example, GSM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
Specified pulse width
Specified pulse width
SCK
SCR write
(CKE0 = 0)
SCR write
(CKE0 = 1)
Figure 14-8 Timing for Fixing Clock Output Level
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 537 of 1458