HD64F2638F20J Datasheet, PDF (614/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 1
IRIC
0
1
Description
Waiting for transfer, or transfer in progress
(Initial value)
[Clearing conditions]
• When 0 is written in IRIC after reading IRIC = 1
• When ICDR is written or read by the DTC
(When the TDRE or RDRF flag is cleared to 0)
(This is not always a clearing condition; see the description of DTC operation for
details)
Interrupt requested
[Setting conditions]
I²C bus format master mode
• When a start condition is detected in the bus line state after a start condition is
issued (when the TDRE flag is set to 1 because of first frame transmission)
• When a wait is inserted between the data and acknowledge bit when WAIT = 1
• At the end of data transfer
(at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th
transmit/receive clock pulse when using wait insertion)
• When a slave address is received after bus arbitration is lost (when the AL flag is
set to 1)
• When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the
ACKB bit is set to 1)
I²C bus format slave mode
• When the slave address (SVA, SVAX) matches (when the AAS and AASX flags
are set to 1)
• and at the end of data transfer up to the subsequent retransmission start condition
or stop condition detection (when the TDRE or RDRF flag is set to 1)
• When the general call address is detected (when FS = 0 and the ADZ flag is set to
1) and at the end of data transfer up to the subsequent retransmission start
condition or stop condition detection (when the TDRE or RDRF flag is set to 1)
• When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the
ACKB bit is set to 1)
• When a stop condition is detected (when the STOP or ESTP flag is set to 1)
Synchronous serial format
• At the end of data transfer (when the TDRE or RDRF flag is set to 1)
• When a start condition is detected with serial format selected
When any other condition arises in which the TDRE or RDRF flag is set to 1
Page 564 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010