HD64F2638F20J Datasheet, PDF (238/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 7 Bus Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
7.9 Resets and the Bus Controller
In a reset, the chip, including the bus controller, enters the reset state at that point, and an
executing bus cycle is discontinued.
Page 188 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010