HD64F2638F20J Datasheet, PDF (769/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 19 Motor Control PWM Timer
Bit 4—Compare Match Flag (CMF): Bit 4 indicates the occurrence of a compare match with the
PWCYR register for the corresponding channel.
Bit 4: CMF
0
1
Description
[Clearing conditions]
(Initial value)
• When 0 is written to CMF after reading CMF = 1
• When the DTC is activated by a compare match interrupt, and the DISEL bit in
the DTC’s MRB register is 0
[Setting condition]
• When PWCNT = PWCYR
Bit 3—Counter Start (CST): Bit 3 selects starting or stopping of the PWCNT counter for the
corresponding channel.
Bit 3: CST
0
1
Description
PWCNT is stopped
PWCNT is started
(Initial value)
Bits 2 to 0—Clock Select (CKS): Bits 2 to 0 select the clock for the PWCNT counter in the
corresponding channel.
Bit 2: CKS2
0
1
Bit 1: CKS1
0
1
*
Bit 0: CKS0
0
1
0
1
*
Description
Internal clock: counts on φ/1
Internal clock: counts on φ/2
Internal clock: counts on φ/4
Internal clock: counts on φ/8
Internal clock: counts on φ/16
(Initial value)
*: Don’t care
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 719 of 1458