HD64F2638F20J Datasheet, PDF (835/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
H'000000
EB0
H'000400
EB1
H'000800
EB2
H'000C00
EB3
H'001000
Section 21A ROM
(H8S/2636 Group)
This area can be accessed
from both the RAM area
and flash memory area
Flash memory
EB4 to EB9
H'FFE000
H'FFE3FF
H'01FFFF
On-chip RAM
H'FFEFBF
Figure 21A-16 Example of RAM Overlap Operation
Example in which Flash Memory Block Area EB0 is Overlapped
1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the
area (EB0) for which real-time programming is required.
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB0).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting
the P or E bit in flash memory control register 1 (FLMCR1), will not cause a transition
to program mode or erase mode. When actually programming or erasing a flash
memory area, the RAMS bit should be cleared to 0.
2. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm while flash memory emulation in RAM is being used.
3. Block area EB0 contains the vector table. When performing RAM emulation, the
vector table is needed in the overlap RAM.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 785 of 1458