HD64F2638F20J Datasheet, PDF (686/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 Controller Area Network (HCAN)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
16.2.12 Mailbox Interrupt Mask Register (MBIMR)
The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing
flags that enable or disable individual mailbox (buffer) interrupt requests.
MBIMR
Bit: 15
14
13
12
11
10
9
8
MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 0—Mailbox Interrupt Mask (MBIMRx): Flags that enable or disable individual
mailbox interrupt requests.
Bit x: MBIMRx
0
1
Description
[Transmitting]
• Interrupt request to CPU due to TXPR clearing
[Receiving]
• Interrupt request to CPU due to RXPR setting
Interrupt requests to CPU disabled
(Initial value)
(x = 15 to 0)
Page 636 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010