HD64F2638F20J Datasheet, PDF (1449/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
SSR0—Serial Status Register 0
SSR1—Serial Status Register 1
SSR2—Serial Status Register 2
H'FF7C
H'FF84
H'FF8C
Smart Card Interface 0
Smart Card Interface 1
Smart Card Interface 2
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Multiprocessor Bit Transfer
Transmit End
0 Transmission is in progress
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and write data to TDR
1 Transmission has ended
[Setting conditions]
• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 1
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 1
0 Data with a 0 multi-processor
bit is transmitted
1 Data with a 1 multi-processor
bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
• When data with a 0 multiprocessor
bit is received*⁵
1 [Setting condition]
• When data with a 1 multiprocessor
bit is received
Note: etu: Elementary time unit (time for transfer of 1 bit)
Parity Error
0 [Clearing condition]
• When 0 is written in PER after reading PER = 1*³
1 [Setting condition]
• When, in reception, the number of 1 bits in the receive data plus the parity bit *⁴
does not match the parity setting (even or odd) specified by the O/E bit in SMR
Error Signal Status
0 Normal reception, with no error signal
[Clearing conditions]
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
1 Error signal sent from receiver indicating detection of parity error
[Setting condition]
• When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag,
which retains its previous state.
Overrun Error
0 [Clearing condition]
• When 0 is written in ORER after reading ORER = 1*¹
1 [Setting condition]
• When the next serial reception is completed while RDRF = 1*²
Receive Data Register Full
0 [Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
• When serial reception ends normally and receive data is transferred from RSR to RDR
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Transmit Data Register Empty
0 [Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1399 of 1458