HD64F2638F20J Datasheet, PDF (132/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 3 MCU Operating Modes
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
INTM1
0
1
Bit 4
INTM0
0
1
0
1
Interrupt Control
Mode
Description
0
Control of interrupts by I bit
(Initial value)
—
Setting prohibited
2
Control of interrupts by I2 to I0 bits and IPR
—
Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
0
1
Description
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
(Initial value)
Bit 2— Reserved: Only 0 should be written to this bit.
Bit 1—Reserved: This bit is always read as 0 and cannot be modified.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Note: When the DTC is used, the RAME bit must not be cleared to 0.
(Initial value)
Page 82 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010