HD64F2638F20J Datasheet, PDF (486/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
12.2.3 Reset Control/Status Register (RSTCSR)
Bit
:
7
6
5
4
3
2
1
0
WOVF RSTE RSTS
—
—
—
—
—
Initial value :
0
0
0
1
1
1
1
1
R/W
: R/(W)^* R/W
R/W
—
—
—
—
—
Note: * Can only be written with 0 for flag clearing.
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 12.2.4, Notes on Register Access.
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
0
1
Description
[Clearing condition]
(Initial value)
• Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
[Setting condition]
• Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2636 if TCNT overflows during watchdog timer operation.
Bit 6
RSTE
Description
0
Reset signal is not generated if TCNT overflows^*
(Initial value)
1
Reset signal is generated if TCNT overflows
Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset.
Page 436 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010