HD64F2638F20J Datasheet, PDF (715/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 16 Controller Area Network (HCAN)
16.3.4 Receive Mode
Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is
described below, and a reception flowchart is shown in figure 16-9.
Initialization (after hardware reset only)
a. Clearing of IRR0 bit in interrupt register (IRR)
b. Bit rate settings
c. Mailbox transmit/receive settings
d. Mailbox (RAM) initialization
Interrupt and receive message settings
a. CPU interrupt source setting
b. Arbitration field setting
c. Local acceptance filter mask (LAFM) settings
Message reception and interrupts
a. Message reception CRC check
b. Data frame reception
c. Remote frame reception
d. Unread message reception
Initialization (After Hardware Reset Only): These settings should be made while the HCAN is
in bit configuration mode.
• IRR0 clearing
The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby
mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0
should be cleared.
• Bit rate settings
Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit
Rate and Bit Timing Settings in 16.3.2, Initialization after Hardware Reset, for details.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 665 of 1458