HD64F2638F20J Datasheet, PDF (199/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 7 Bus Controller
Section 7 Bus Controller
7.1 Overview
The chip has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas. The bus specifications, such as bus width and number of access states, can be set
independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU, and data transfer controller (DTC).
Note: The DTC is not implemented in the H8S/2635 Group.
7.1.1 Features
The features of the bus controller are listed below.
• Manages external address space in area units
⎯ Manages the external space as 8 areas of 2-Mbytes
⎯ Bus specifications can be set independently for each area
⎯ Burst ROM interface can be set
• Basic bus interface
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
• Burst ROM interface
⎯ Burst ROM interface can be set for area 0
⎯ Choice of 1- or 2-state burst access
• Idle cycle insertion
⎯ An idle cycle can be inserted in case of an external read cycle between different areas
⎯ An idle cycle can be inserted in case of an external write cycle immediately after an
external read cycle
• Write buffer functions
⎯ External write cycle and internal access can be executed in parallel
• Bus arbitration function
⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC
• Other features
⎯ External bus release function
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 149 of 1458