HD64F2638F20J Datasheet, PDF (713/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 16 Controller Area Network (HCAN)
When a is selected, if a number of messages are designated as waiting for transmission (TXPR
= 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order:
mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the
transmit buffer, and message transmission is performed when the bus is acquired.
When b is selected, if a number of messages are designated as waiting for transmission (TXPR
= 1), the message with the highest priority set in the message identifier (MCx[5] to MCx[8]) is
stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the
transmit buffer, and message transmission is performed when the transmission right is
acquired. When the TXPR bit is set, internal arbitration is performed again, the highest-priority
message is found and stored in the transmit buffer, CAN bus arbitration is carried out in the
same way, and message transmission is performed when the transmission right is acquired.
• Message transmission completion and interrupt
When a message is transmitted error-free using the above procedure, the corresponding
acknowledge bit (TXACK1 to TXACK15) in the transmit acknowledge register (TXACK) and
transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) are automatically
initialized. Also, if the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt
mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask
register (IMR) are set to the interrupt enable state at the same time, an interrupt can be sent to
the CPU.
• Message transmission cancellation
Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait
message. A transmit wait message is canceled by setting the bit for the corresponding mailbox
(TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is
executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is
set to 1 in the abort acknowledge register (ABACK). An interrupt can be requested. Also, if
the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1 to MBIMR15)
corresponding to the mailbox interrupt mask register (MBIMR) and interrupt mask register
(IMR), interrupts may be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
a. During internal arbitration or CAN bus arbitration
b. During data frame or remote frame transmission
Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure
16-5 shows a flowchart of transmit message cancellation.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 663 of 1458