HD64F2638F20J Datasheet, PDF (33/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

7.4 Basic Bus Interface ........................................................................................................... 167
7.4.1 Overview.............................................................................................................. 167
7.4.2 Data Size and Data Alignment............................................................................. 167
7.4.3 Valid Strobes........................................................................................................ 169
7.4.4 Basic Timing........................................................................................................ 170
7.4.5 Wait Control ........................................................................................................ 178
7.5 Burst ROM Interface......................................................................................................... 179
7.5.1 Overview.............................................................................................................. 179
7.5.2 Basic Timing........................................................................................................ 179
7.5.3 Wait Control ........................................................................................................ 181
7.6 Idle Cycle .......................................................................................................................... 181
7.6.1 Operation ............................................................................................................. 181
7.6.2 Pin States During Idle Cycles .............................................................................. 185
7.7 Write Data Buffer Function .............................................................................................. 186
7.8 Bus Arbitration.................................................................................................................. 187
7.8.1 Overview.............................................................................................................. 187
7.8.2 Operation ............................................................................................................. 187
7.8.3 Bus Transfer Timing ............................................................................................ 187
7.9 Resets and the Bus Controller ........................................................................................... 188
Section 8 Data Transfer Controller (DTC)................................................................... 189
8.1 Overview........................................................................................................................... 189
8.1.1 Features................................................................................................................ 189
8.1.2 Block Diagram..................................................................................................... 190
8.1.3 Register Configuration......................................................................................... 191
8.2 Register Descriptions ........................................................................................................ 192
8.2.1 DTC Mode Register A (MRA) ............................................................................ 192
8.2.2 DTC Mode Register B (MRB)............................................................................. 194
8.2.3 DTC Source Address Register (SAR).................................................................. 195
8.2.4 DTC Destination Address Register (DAR).......................................................... 195
8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 195
8.2.6 DTC Transfer Count Register B (CRB)............................................................... 196
8.2.7 DTC Enable Registers (DTCER) ......................................................................... 196
8.2.8 DTC Vector Register (DTVECR)........................................................................ 197
8.2.9 Module Stop Control Register A (MSTPCRA) ................................................... 199
8.3 Operation .......................................................................................................................... 200
8.3.1 Overview.............................................................................................................. 200
8.3.2 Activation Sources ............................................................................................... 202
8.3.3 DTC Vector Table ............................................................................................... 204
8.3.4 Location of Register Information in Address Space ............................................ 208
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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