HD64F2638F20J Datasheet, PDF (636/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
receive operation has finished, perform the issue stop condition processing described in step
[15] below.
[14] If the IRTR flag value is 0, clear the IRIC flag to 0 to cancel the wait state. Return to reading
the IRIC flag, as described in step [12], to detect the end of the receive operation.
[15] Clear the WAIT bit in ICMR to 0 to cancel the wait mode. Then clear the IRIC flag to 0. The
IRIC flag should be cleared when the value of WAIT is 0 (The stop condition may not be
output properly when the issue stop condition instruction is executed if the WAIT bit was
cleared to 0 after the IRIC flag is cleared to 0).
[16] Read the final receive data in ICDR.
[17] Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
Master transmit mode
SCL
(master output) ⁹
SDA
(slave output)
A
SDA
(master output)
IRIC
IRTR
ICDR
Master receive mode
1234567 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3]
A
912345
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
[3]
Data 2
[4] IRTR = 0
[4] IRTR = 1
Data 1
User processing
[2] ICDR read (dummy read)
[1] TRS cleared to 0
IRIC clearance
[6] IRIC clearance _{[5] ICDR read} [6] IRIC clearance
(cancel wait)
(data 1)
Figure 15-12 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
Page 586 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010