HD64F2638F20J Datasheet, PDF (790/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 20 RAM
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
20.2 Register Descriptions
20.2.1 System Control Register (SYSCR)
Bit
:
Initial value :
R/W
:
7
MACS
0
R/W
6
5
4
3
2
⎯ INTM1 INTM0 NMIEG ⎯
0
0
0
0
0
⎯
R/W R/W R/W R/W
1
0
⎯ RAME
0
1
⎯
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
20.3 Operation
When the RAME bit is set to 1, accesses to addresses H'FFE000 to H'FFEFBF (for the H8S/2636),
H'FFB000 to H'FFEFBF (for the H8S/2638, H8S/2639, and H8S/2630), H'FFD800 to H'FFEFBF
(for the H8S/2635 Group), or H'FFFFC0 to H'FFFFFF in the chip are directed to the on-chip
RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to
and read in byte or word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
Page 740 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010