HD64F2638F20J Datasheet, PDF (17/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Item
Page
21B.9.1 Program Mode 826
21B.9.2 Program-
830
Verify Mode
Figure 21B-12
Program/Program-
Verify Flowchart
21B.9.3 Erase Mode 831
Revision (See Manual for Details)
Description amended
The wait times after bits are set or cleared in the flash memory
control register 1 (FLMCR1) and the maximum number of
programming operations (N) are shown in section 24.2.7,
24.3.7, and 24.4.7, Flash Memory Characteristics.
Figure amended
No
m=0?
Yes
Clear SWE bit in FLMCR1
Wait (tcswe) μs
*7
End of programming
*7 _No
n ≥ (N)?
Yes
Clear SWE bit in FLMCR1
Wait (tcswe) μs
*7
Programming failure
Description amended
The wait times after bits are set or cleared in the flash memory
control register 1 (FLMCR1) and the maximum number of
erase operations (N) are shown in section 24.2.7 and 24.3.7,
Flash Memory Characteristics.
…
Next, the watchdog timer (WDT) is set to prevent overerasing
due to program runaway, etc. Set a value of about 19.8 ms as
the WDT overflow period.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page xvii of l