HD64F2638F20J Datasheet, PDF (981/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F,
HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F]
Bit 6
STS2
0
1
Bit 5
STS1
0
1
0
1
Bit 4
STS0
0
1
0
1
0
1
0
1
Description
Standby time = 8192 states
Standby time = 16384 states
Standby time = 32768 states
Standby time = 65536 states
Standby time = 131072 states
Standby time = 262144 states
Reserved
Standby time = 16 states (Setting prohibited)
(Initial value)
Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the
software standby mode.
Bit 3
OPE
0
1
Description
In software standby mode, address bus and bus control signals are high-impedance.
In software standby mode, the output state of the address bus and bus control signals
is retained.
(Initial value)
Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.
23A.2.2 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
PSTOP ⎯
⎯
⎯
Initial value :
0
0
0
0
R/W
: R/W
⎯
⎯
⎯
3
STCS
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
0
SCK0
0
R/W
SCKCR is an 8-bit readable/writable register that performs φ clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 931 of 1458