HD64F2638F20J Datasheet, PDF (261/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 8 Data Transfer Controller (DTC)
8.3.7 Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt is requested.
Table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory
mapping in block transfer mode.
Table 8-7 Register Information in Block Transfer Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Function
Designates source address
Designates destination address
Holds block size
Designates block size count
Transfer count
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 211 of 1458