HD64F2638F20J Datasheet, PDF (532/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 13 Serial Communication Interface (SCI)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
• Serial data reception (asynchronous mode)
Figure 13-7 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
Initialization
Start reception
[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error processing and
break detection:
Read ORER, PER, and
FER flags in SSR
[2]
If a receive error occurs, read the
ORER, PER, and FER flags in
SSR to identify the error. After
PER ∨ FER ∨ ORER = 1
Yes
[3]
performing the appropriate error
processing, ensure that the
ORER, PER, and FER flags are
No
Error processing
all cleared to 0. Reception cannot
be resumed if any of these flags
(Continued on next page) ^{are set to 1. In the case of a}
framing error, a break can be
Read RDRF flag in SSR
[4]
detected by reading the value of
the input port corresponding to
the RxD pin.
No
RDRF= 1
[4] SCI status check and receive
data read :
Yes
Read SSR and check that RDRF
= 1, then read the receive data in
Read receive data in RDR, and
clear RDRF flag in SSR to 0
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
No
All data received?
Yes
Clear RE bit in SCR to 0
<End>
[5]
[5] Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when DTC is activated by an RXI
interrupt and the RDR value is
read.
Figure 13-7 Sample Serial Reception Data Flowchart
Page 482 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010