HD64F2638F20J Datasheet, PDF (1220/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
Bit
7
6
⎯
⎯
Initial value
0
0
Read/Write
⎯
⎯
5
4
3
⎯
IRR12
⎯
0
0
0
⎯
R/W
⎯
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
2
1
0
⎯
IRR9 IRR8
0
0
0
⎯
R
R/W
Mailbox Empty Interrupt Flag
0 [Clearing condition]
• Writing 1
1 Transmit message has been transmitted or aborted, and new message
can be stored
[Setting condition]
• When TXPR (transmit wait register) is cleared by completion of
transmission or completion of transmission abort
Unread Interrupt Flag
0 [Clearing condition]
• Clearing of all bits in UMSR (unread message status register)
1 Unread message overwrite
[Setting condition]
• When UMSR (unread message status register) is set
Bus Operation Interrupt Flag
0 CAN bus idle state
[Clearing condition]
• Writing 1
1 CAN bus operation in HCAN sleep mode
[Setting condition]
• Bus operation (dominant bit detection) in HCAN sleep mode
Page 1170 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010